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October 23-26, 2017 - Prague, Czech Republic
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Monday, October 23 • 12:05 - 12:45
Hardware Deceleration: The Challenges of Speeding Up Software - Kris Chaplin, Altera

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Developing a custom ASIC or making a SoC using FPGAs gives us the potential to make very specific accelerators to speed up software bottlenecks - however, this is not without its challenges! We need to account for cached data and translation from virtual to physical addresses when moving data payloads from user space into the hardware. Moving data from the SoC to the Accelerator and back has the potential of a lot of software overhead before it can even get started.

In this presentation, Kris Chaplin will discuss techniques and hardware mechanisms that allow for hardware accelerators to actually accelerate, rather than slow down a running system with the potential additional overhead they could require.


Monday October 23, 2017 12:05 - 12:45
Congress Hall III
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